Details

Autor(en) / Beteiligte

• Huang, Kai-Ping
• Peng, Po-Lin
• Chu, Li-Wei
• Chang, Yi-Feng
• Chang, Tzu-Heng
• Lee, Jam-Wem
• Chen, Kuo-Ji
• Song, Ming-Hsiang

Titel

ESD protection Diode with Guard Ring Layout Optimized for Latch-up Immunity Enhancement in FinFET technology

Ist Teil von

• 2019 41st Annual EOS/ESD Symposium (EOS/ESD), 2019, Vol.EOS-41, p.1-4

Ort / Verlag

EOS/ESD Association, Inc

Erscheinungsjahr

2019

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• A novel ESD dual diode with stronger latch-up robustness has been proposed in FinFET technology. By inserting PW/NW straps, the proposed ESD diode can be built without changing DC-IV and ESD characteristics of conventional ESD diode. The experimental and simulation results demonstrate that the proposed structure has been successfully verified in FinFET CMOS platform.