Details

Autor(en) / Beteiligte

• Passlack, M
• Ramvall, P
• Vasen, T
• Afzalian, A
• Thelander, C
• Dick, K.A
• Wernersson, L.-E
• Doornbos, G
• Holland, M

Titel

Core-Shell TFET Developments and TFET Limitations

Ist Teil von

• 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2019, p.1-2

Ort / Verlag

IEEE

Erscheinungsjahr

2019

Link zum Volltext

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• Tunneling field-effect transistors (TFET) based on a vertical gate-all-around (VGAA) nanowire (NW) architecture with a core-shell (CS) structure have been explored for future CMOS applications. Performance predictions based on a tight-binding mode-space NEGF technique include a drive current Ion of 6.7 μA (NW diameter d = 10.2 nm) at V dd =0.3 V under low power (LP) conditions (I off =1 pA) for an InAs/GaSb CS TFET. This compares to Si nMOSFET I on = 2.3 μA at V dd =0.55 V(d=6 nm). On the experimental side, scaling of vertical CS NWs resulted in smallest dimensions of d c = 17 nm (GaSb core) and t sh =3 nm (InAs shell) for a total diameter of 23 nm. VGAA CS nFETs demonstrated drive current of up to 40 μA (V d =0.3 V) and subthreshold swing SS=40mV/dec(V d =10mV) for NW diameters between 35 - 50 nm. Although key TFET properties such as current drive and subthermal SS have been demonstrated using a VGAA CS architecture for the first time, experimental results still lag predictions. An intrinsic relationship between band-to band-tunneling (BTBT) and D it related trap assisted tunneling (TAT) was found which imposes challenging D it requirements, in particular for LP I off specifications. Complexity of fabrication and a material system foreign to CMOS manufacturing further impact prospects of TFET technology.