Details

Autor(en) / Beteiligte

• Liu, S. E.
• Hsieh, M. H.
• Chen, Y. R.
• Jao, J. Y.
• Lin, M. Z.
• Fang, Y. H.
• Lin, M. J.

Titel

High Voltage Tolerant Design with Advanced Process for TV Application

Ist Teil von

• 2019 IEEE International Reliability Physics Symposium (IRPS), 2019, p.1-4

Ort / Verlag

IEEE

Erscheinungsjahr

2019

Quelle

IEEE/IET Electronic Library

Beschreibungen/Notizen

• High voltage tole rant IO interface provides an efficient and flexible solution for integrated multimedia application. In this paper, we studied the design for reliability of IO interface in advanced technology node. Three different approaches, which is from device, layout and circuit point of view, to enhance the IO overdrive circuit (IP) reliability are investigated. We successfully develop a LDMOS that is compatible with advanced process and provides good reliability. However, new device development is a time consuming process. To reduce time-to-market, two solutions are proposed. 1) Taking the advantage of reverse body bias effect to reduce HCI damage on IP level. It can be achieved by implementing deep N-well. 2) Reducing the overstress voltage on devices by bias tracing circuit. Finally, we compared the IO interface performance and area of each solution. The solution with bias tracing circuit exhibits good reliability to sustain 5V stress and provides 66% area reduction.