Details

Autor(en) / Beteiligte

• Jha, Kamini
• Patil, Ajit. B.
• Khurge, Deepti. S.

Titel

Design and Verification of LTSSM in USB 3.0

Ist Teil von

• 2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA), 2018, p.1-4

Ort / Verlag

IEEE

Erscheinungsjahr

2018

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• At present as technology is increasing rapidly, communication have become an important part of digital world. The fact that exchange of data is increasing with a greater reliability of high performance and processing speed the USB protocol engine have made an attempt to establish itself in the field of digital communications with all of the necessary protocol layers with excellent features and specifications which enable the flow of data very smoothly. The architecture for USB 3.0 provided will increase the USB overall speed and performance with having layered protocol architecture. USB 3.0, LTSSM includes the physical and link layer which includes greater superspeed functionality than the previous version. USB 3.0 protocol is used generally for connecting PCs to peripheral devices, supporting data transferring rate of 5 Gbit/s. In this paper design of LTSSM which consists of 12 link states has been explained. Also Verification of LTTSM has been done using System Verilog. All simulations are done using Mentor Graphics Tool. Functional verification for LTSSM has been done.