Details

Autor(en) / Beteiligte

• Mochida, Reiji
• Kouno, Kazuyuki
• Hayata, Yuriko
• Nakayama, Masayoshi
• Ono, Takashi
• Suwa, Hitoshi
• Yasuhara, Ryutaro
• Katayama, Koji
• Mikawa, Takumi
• Gohou, Yasushi

Titel

A 4M Synapses integrated Analog ReRAM based 66.5 TOPS/W Neural-Network Processor with Cell Current Controlled Writing and Flexible Network Architecture

Ist Teil von

• 2018 IEEE Symposium on VLSI Technology, 2018, p.175-176

Ort / Verlag

IEEE

Erscheinungsjahr

2018

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE/IET Electronic Library (IEL)

Beschreibungen/Notizen

• This paper presents low-power neural-network (NN) processor using ReRAM to store weights as analog resistance for future AI computing. We propose ReRAM perceptron circuit for realizing large scale integration, highly accurate cell current controlled writing scheme, and flexible network architecture (FNA) in which any NNs can be configured. Fabricated 180nm test chip shows well-controlled analog cell current with linear 30μA dynamic range and 0.59μA variation of 1 sigma, results in 90.8% MNIST numerical recognition rate. Furthermore, 4M synapses integrated 40nm test chip achieves lower analog cell current and 66.5 TOPS/W power efficiency.