Details

Autor(en) / Beteiligte

• Tang, Junyao
• Zhan, Chenchang
• Wang, Guanhua
• Liu, Yang

Titel

A 0.7V Fully-on-Chip Pseudo-Digital LDO Regulator with 6.3μA Quiescent Current and 100mV Dropout Voltage in 0.18-μm CMOS

Ist Teil von

• ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), 2018, p.206-209

Ort / Verlag

IEEE

Erscheinungsjahr

2018

Link zum Volltext

• IEEE_Xplore

Quelle

IEL

Beschreibungen/Notizen

• This paper presents an NMOS pseudo-digital low-dropout (PD-LDO) regulator that supports low-voltage operation by eliminating the amplifier of an analog LDO. The proposed pseudo-digital control loop consists of a latched comparator, a 2X charge pump and a RC network. It detects the output voltage and provides a continuous gate control signal for the power transistor by charging and discharging the RC network. Fast transient response is achieved due to the source follower structure of the power NMOS, with a small output capacitor and small occupied chip area and without consuming large quiescent current. The proof-of-concept design of the proposed PD-LDO is implemented in a 0.18-J.1m CMOS process. The minimum supply voltage is 0.7 V, with a dropout voltage of 100 mV and a maximum load current of 100 mA. Using only 20 pF of on-chip output capacitor and 10 MHz comparator clock frequency, the undershoot is 106 mV with 90 mA load current step and 150 ns edge time. The quiescent current is only 6.3 μA and the active chip area is 0.08 mm 2 .