Details

Autor(en) / Beteiligte

• Ni, Kai
• Li, Xueqing
• Smith, Jeffrey A.
• Jerry, Matthew
• Datta, Suman

Titel

Write Disturb in Ferroelectric FETs and Its Implication for 1T-FeFET AND Memory Arrays

Ist Teil von

• IEEE electron device letters, 2018-11, Vol.39 (11), p.1656-1659

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2018

Quelle

IEEE Xplore

Beschreibungen/Notizen

• In this letter, the write disturb of Hf 0.5 Zr 0.5 O 2 -based 1T-FeFET nonvolatile AND memory array is experimentally investigated for <inline-formula> <tex-math notation="LaTeX">{V}_{W} </tex-math></inline-formula>/2 and <inline-formula> <tex-math notation="LaTeX">{V}_{W} </tex-math></inline-formula>/3 inhibition bias schemes to determine the worst-case memory sensing condition. Read margin analysis reveals that the increased leakage current in the low-<inline-formula> <tex-math notation="LaTeX">{V}_{\textsf {TH}} </tex-math></inline-formula> erased state and the increased read current of the high-<inline-formula> <tex-math notation="LaTeX">{V}_{\textsf {TH}} </tex-math></inline-formula> programmed state are the key factors that limit the maximum array size.