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Design and Simulation of a CMOS Slew-Rate Enhanced OTA to Drive Heavy Capacitive Loads
Ist Teil von
2018 International Conference on Biomedical Engineering and Applications (ICBEA), 2018, p.1-6
Ort / Verlag
IEEE
Erscheinungsjahr
2018
Link zum Volltext
Quelle
IEL
Beschreibungen/Notizen
Flicker noise is one of the main noise contributors in CMOS Image Sensors. After great effort from universities and industry in reducing thermal noise, in modern CMOS imagers the bottleneck in achieving lower noise performance is now flicker noise. This paper presents a new method to reduce the flicker noise contribution in the overall sensor noise budget by means of reducing the time for Double Sampling, so that it more effectively filters the flicker noise spectrum introduced by the pixel source follower amplifier. In addition, this paper also proposes a way to promote and ensure no column induced lag from column readout circuitry through strong and stable references. The proposed amplifier circuit buffers the reference voltage while Double Sampling operation performed in the analogue domain, is taking place. It not only shortens the time between samples, but also reduces the current consumption, reducing part of the sensor power heat dissipation. Finally, the proposed architecture can be used in different applications where high resolution and stable references are needed, e.g. to supply the references for massive column parallel analogue circuits which are typical in modern CMOS Image Sensor designs. The design and simulation of the proposed high Slew-Rate driver circuit are verified with a circuit containing 3000 readout columns.