Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
Using discrete wavelet transform (DWT) in highspeed signal processing applications imposes a high degree of care to hardware resource availability, latency and power consumption. In this paper, we investigate the design and implementation aspects of 1-level DWT by employing a finite impulse response (FIR) filter on FPGA platform. FPGAs come with a limited number of multipliers, which restricts the size and number of DWT levels. As a result, a multiplication-free architecture becomes a necessity for implementing large DWT. Our goal is to estimate the performance requirements and hardware resources for two key multiplication-free architectures, namely, distributed arithmetic algorithm (DAA) and residue number system (RNS), allowing for selection of the proper algorithm and implementation of DAA and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex-6 ML605 FPGA, taking advantage of Virtex-6's embedded block RAMs (BRAMs). The results show that the DAA-based approach is appropriate and feasible for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps.