2017 IEEE International Electron Devices Meeting (IEDM), 2017, p.21.6.1-21.6.4
2017
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Details
- Autor(en) / Beteiligte
- Titel
- Overcoming the reliability limitation in the ultimately scaled DRAM using silicon migration technique by hydrogen annealing
- Ist Teil von
- 2017 IEEE International Electron Devices Meeting (IEDM), 2017, p.21.6.1-21.6.4
- Ort / Verlag
- IEEE
- Erscheinungsjahr
- 2017
- Quelle
- IEEE Xplore
- Beschreibungen/Notizen
- We demonstrated a highly reliable buried-gate saddle-fin cell-transistor (cell-TR) using silicon migration technique of hydrogen (H 2 ) annealing after a dry etch to form the saddle-fin in a fully integrated 2y-nm 4Gb DRAM. It clearly shows a reduction in interface trap density with highly enhanced variable-retention-time (VRT) and Row-Hammering immunity.
- Sprache
- Englisch
- Identifikatoren
- eISSN: 2156-017XDOI: 10.1109/IEDM.2017.8268437Titel-ID: cdi_ieee_primary_8268437
- Format
- –
- Schlagworte
- Fabrication, Hafnium, hydrogen anneal, interface trap VRT and Row-Hammering, Random access memory, saddle finfet