Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
Energy-efficient standby current suppression with bootstrapped power-gating technique
Ist Teil von
2017 IEEE 12th International Conference on ASIC (ASICON), 2017, p.464-467
Ort / Verlag
IEEE
Erscheinungsjahr
2017
Quelle
IEEE Xplore
Beschreibungen/Notizen
This paper presents a bootstrapped power-gating technique for suppressing standby current using a modified dynamic standby control (DSC). The modified DSC recharges the gate voltage by a keeper, which maintains the power gates cut-off with negative overdrive voltage. In order to achieve high energy-efficiency, a current sensor is used to observe total standby current on power gates and DSC. Based on the current sensor, the minimal standby current can be found even in different PVT corners. The bootstrapped power-gating technique is simulated in 65nm CMOS process. According to simulation results, energy-efficient standby current can be found by adjusting the recharging rate of DSC.