Details

Autor(en) / Beteiligte

• Akram, Muhammad Abrar
• Hong, Wook
• Hwang, In-Chul

Titel

Fast Transient Fully Standard-Cell-Based All Digital Low-Dropout Regulator With 99.97% Current Efficiency

Ist Teil von

• IEEE transactions on power electronics, 2018-09, Vol.33 (9), p.8011-8019

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2018

Quelle

IEEE Xplore

Beschreibungen/Notizen

• A fully standard-cell-based digital low-dropout (D-LDO) regulator with low-level quiescent current and fast load transient response is proposed for efficient power management in a system-on-a-chip. For the design of a fast and accurate voltage comparator, we propose a logic-threshold triggered comparator (LTTC) based on a standard CMOS digital inverter. The LTTC is employed to implement the binary voltage comparator for a bang-bang loop control and a multimode detector, which senses the output voltage with three segmented ranges during its transition, is also employed. Further, we implement a multiloop controller composed of components, such as a fixed-gain accumulator, successive approximation register, and variable-gain accumulator (VG-ACC), which accelerate the transient response while being switched over adaptively to the finely segmented voltage range. In particular, the proposed VG-ACC enables a constant unity-gain frequency overload current variation such that it enhances the load transient response in terms of over/undershoot and settling time. The proposed D-LDO is fabricated using a 65-nm CMOS process technology with an active area of 0.014 mm 2 . The measurement results show a peak current efficiency of 99.97% with the enhanced load-transient response and load regulation of 2.08 μs and 0.040 mV/mA, respectively, with a 20-MHz clock.