Details

Autor(en) / Beteiligte

• Shen-Li Chen
• Yi-Cih Wu
• Chih-Hung Yang
• Chih-Ying Yen
• Kuei-Jyun Chen
• Jia-Ming Lin
• Yi-Hao Chiu
• Yu-Lin Lin
• Chun-Ting Kuo
• Jen-Hao Lo
• Yi-Hao Chao
• Hung-Wei Chen

Titel

Source-end design and failure study for ESD enhancement of 60 V nLDMOS devices

Ist Teil von

• 2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2017, p.1-4

Ort / Verlag

IEEE

Erscheinungsjahr

2017

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• In this work, ESD immunity enhancement for the HV n-channel LDMOS with source-end discrete islands fabricated by a TSMC 0.25 μm 60 V process was investigated. An nLDMOS device always has poor ESD capability. If discrete n + islands are formed in the source end of an nLDMOS transistor, the It 2 value of this DUT is upgraded by 4.92% as compared with that of the reference nLDMOS. Meanwhile, if an nLDMOS is embedded with an SCR with an npn (pnp) stripe manner in the drain end, the corresponding I t2 can be enhanced by 14.8% (30%) as compared with those of the reference nLDMOS. Moreover, if source-end discrete islands are designed into an npn-arranged (pnp-arranged) nLDMOS-SCR, the maximum I t2 values are improved by 24.6% (>282.5%). Then, an nLDMOS incorporating discrete n + islands in the source end will be effective in enhancing ESD reliability.