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With the increase in usage of low-power electronics in security critical area, demand for secure transmission of private and confidential information is on the rise. Implementation of dedicated hardware for cryptography is essential nowadays, even in the resource-constrained devices, to meet high-security concerns. However, hardware implementation of cryptographic algorithms may result in security vulnerabilities. Scan-chain-based attack (SBA), fault-injection attack (FIA), and power analysis attack (PAA) are three popular cryptanalysis techniques in exploiting vulnerabilities of crypto-chips. Employing multiple strategies for counteracting the attacks results in significant resource overheads in the cryptographic chips. In this paper, we present a novel and solitary approach to prevent either type of attacks on the hardware implementation of Advanced Encryption Standard (AES). Two additional layers, controlled by true random number generator, are introduced in the proposed technique to conceal sensitive data stored in memory bank. One layer permutes and masks intermediate state before storing in registers, and the other layer is used to reconstruct intermediate state at the start of the round operations of AES. With a two-third increase in resource overhead and negligible increase in timing overhead compared to the regular AES datapath, the proposed technique makes the system resilient against SBA, FIA as well as PAA.