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2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4
2017
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Autor(en) / Beteiligte
Titel
Design of an SVD engine for 8×8 MIMO precoding systems
Ist Teil von
  • 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4
Ort / Verlag
IEEE
Erscheinungsjahr
2017
Quelle
IEEE/IET Electronic Library
Beschreibungen/Notizen
  • A singular-value-decomposition (SVD) engine for 8×8 MIMO precoding systems is designed and implemented. The memory-based architecture is adopted with eight processing elements, each having two CORDIC modules. Two-phase operations are performed including bidiagonalization and Golub-Reinsch SVD (GR-SVD) with Rayleigh quotient shift. The split, deflation, and shift techniques of GR-SVD can effectively decrease the processed matrix size and accelerate the diagonalization to enhance the throughput. To cover the wide distribution of singular vector elements and singular values derived from 8 × 8 MIMO channel matrix, hybrid datapath representations are used. The thresholds for split and deflation can be adjusted and thus the accuracy of the SVD engine is variable according to the requirements. From the synthesis results, the SVD engine in 45nm CMOS technology is able to provide the throughput rate of 636K matrix/s and outperforms the previous design.
Sprache
Englisch
Identifikatoren
eISSN: 2379-447X
DOI: 10.1109/ISCAS.2017.8050313
Titel-ID: cdi_ieee_primary_8050313

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