Details

Autor(en) / Beteiligte

• Ben Thameur, Hayfa
• Le Gal, Bertrand
• Khouja, Nadia
• Tlili, Fethi
• Jego, Christophe

Titel

A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures

Ist Teil von

• 2017 IEEE Symposium on Computers and Communications (ISCC), 2017, p.898-905

Ort / Verlag

IEEE

Erscheinungsjahr

2017

Link zum Volltext

Quelle

IEEE Xplore Digital Library

Beschreibungen/Notizen

• Low-density parity-check convolutional codes (LDPC-CC) have interesting error correction features. They have a great potential to become a key error-correcting codes for enhancing reliability of modern digital communication systems, optical systems and storage devices. On the implementation side, however, the design of low-cost low-power and high-throughput LDPC-CC decoders remains challenging. This survey paper provides an overview of the state-of-the-art of different algorithmic optimizations proposed to ease and improve the LDPC-CC decoder implementations. To this end, a summary of the available decoding scheduling approaches is provided. Besides, a complexity analysis, performance comparison and an architectural analysis of LDPC-CC decoders based on different scheduling techniques is detailed.