Details

Autor(en) / Beteiligte

• Chung, Yung-Hui
• Yen, Chia-Wei

Titel

An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS

Ist Teil von

• IEEE transactions on very large scale integration (VLSI) systems, 2017-12, Vol.25 (12), p.3434-3443

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2017

Quelle

IEEE/IET Electronic Library (IEL)

Beschreibungen/Notizen

• This paper presents an 11-bit successive approximation register (SAR) analog-to-digital converter (ADC). The subranged-SAR ADC architecture is applied to achieve a sampling rate of 100 MHz. The proposed gain error compensation helps attenuate the gain error between coarse and fine ADCs. An up-then-down digital-to-analog converter (DAC) switching scheme is used to maintain a small common-mode variation for the fine comparator. To maintain a good spurious free dynamic range (SFDR), the capacitor-swapping scheme is applied in the DAC. The prototype ADC was implemented using a 65-nm CMOS technology. It consumes a total power of 2.4 mW from a 1.2-V supply. The measured peak signal-to-noise-and-distortion ratio and SFDR are 61.1 and 85 dB, respectively. The peak effective number of bits is 9.86, equivalent to a figure-of-merit of 25.8 fJ/conversion step.