Details

Autor(en) / Beteiligte

• Jangam, SivaChandra
• Pal, Saptadeep
• Bajwa, Adeel
• Pamarti, Sudhakar
• Gupta, Puneet
• Iyer, Subramanian S.

Titel

Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

Ist Teil von

• 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, p.86-94

Ort / Verlag

IEEE

Erscheinungsjahr

2017

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• In this paper, we describe the performance and power benefits of our Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF). Here we propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. We show the dramatic improvements in bandwidth, latency, and power are achievable through our integration scheme where small dielets (1-25 mm2) are attached to a rigid Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 μm) and short inter-die distance (50-500 μm) using solderless metal-to-metal thermal compression bonding (TCB). Our simulations show that links in the Si-IF with short wire-lengths (5-25x improvement in data bandwidth. This can improve system performance (>20x) when compared to PCB-style integration and may even approach single die SoC metrics in some cases. Furthermore our protocol is simple and non-proprietary. We show that this scheme enables heterogeneous system integration using a dielet based assembly method and provides significant reduction in design and validation cost.System-level analysis of heterogeneous integration scheme promises power benefits of more than 15% even for very small systems.