Details

Autor(en) / Beteiligte

• Wen-Shuai Bai
• Meng-Long Wu
• Jin Wu
• Dan-Yu Wu
• Lei Zhou

Titel

A calibration technology for 6 Bit 30 Gsps ADC

Ist Teil von

• 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2016, p.900-902

Ort / Verlag

IEEE

Erscheinungsjahr

2016

Quelle

IEEE Xplore

Beschreibungen/Notizen

• An off-chip calibration technology for the 6 Bit 30 Gsps time-interleaved ADC is presented in paper. The mismatches errors are calculated by calibration algorithm base on statistical approximation method. Negative feedback is used to reduce the three mismatches (skew, offset and gain mismatch). The off-chip calibration technology is implemented by FPGA. The measured results show that the average ENOB (Effective Number of Bits) is improved by 0.58, and the average SFDR (Spurious-Noise-Free Dynamic Range) is increased by 11.28dBc.