Details

Autor(en) / Beteiligte

• Sam Yang
• Yanxiang Liu
• Ming Cai
• Jerry Bao
• Peijie Feng
• Xiangdong Chen
• Lixin Ge
• Jun Yuan
• Jihong Choi
• Ping Liu
• Youseok Suh
• Hao Wang
• Jie Deng
• Yandong Gao
• Yang, Jackie
• Xiao-Yong Wang
• Da Yang
• Zhu, John
• Penzes, Paul
• Song, S. C.
• Park, Chulyong
• Sungwon Kim
• Jedon Kim
• Sunggun Kang
• Terzioglu, Esin
• Ken Rim
• Chidi Chidambaram, P. R.

Titel

10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling

Ist Teil von

• 2017 Symposium on VLSI Technology, 2017, p.T70-T71

Ort / Verlag

JSAP

Erscheinungsjahr

2017

Quelle

IEEE Xplore

Beschreibungen/Notizen

• The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AI, machine learning, and computing. 10nm FinFet technology scaling challenges such as sharply increased wiring resistance and variation and strong layout stress effects are discussed to illustrate design and technology co-development from technology definition to product ramp stage is imperative to realize scaling entitlements.