Details

Autor(en) / Beteiligte

• Ben Thameur, Hayfa
• Bouzouita, Chaima
• Khouja, Nadia
• Le Gal, Bertrand
• Tlili, Fethi
• Jego, Christophe

Titel

Hardware complexity reduction of LDPC-CC decoders based on message-passing approaches

Ist Teil von

• 2016 17th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA), 2016, p.679-684

Ort / Verlag

IEEE

Erscheinungsjahr

2016

Quelle

IEEE/IET Electronic Library (IEL)

Beschreibungen/Notizen

• LDPC convolutional codes (LDPC-CC) are a family of error-correcting codes (ECC) used in digital communication systems like the IEEE 1901 standard. High throughput and low complexity hardware architectures were designed for real time systems. In this article we demonstrate that an efficient selection of the message passing (MP) algorithm for LDPC-CC decoding improves the architecture features of related works. In fact, considering the LDPC-CC decoders proposed for the IEEE 1901 standard, we show that an appropriate Min-Sum approximation selection can significantly improve the error correction performance by 0.1 to 0.2 dB in terms of Bit Error Ratio. It can also reduce the hardware complexity by 10% to 20% with no impact on the Bit Error Ratio performance.