Details

Autor(en) / Beteiligte

• Lee, Leo
• Kang, Lewis
• Kwon, Yong Tae
• Kim, T.H.
• Kim, J.H.
• Lee, E.J.
• Lee, J.K.

Titel

FOWLP technology as wafer level system in packaging (SiP) solution

Ist Teil von

• 2017 International Conference on Electronics Packaging (ICEP), 2017, p.491-493

Ort / Verlag

Japan Institute of Electronics Packaging

Erscheinungsjahr

2017

Quelle

IEEE Explore

Beschreibungen/Notizen

• The market of Connectivity, Internet of Things (IoT), Wearable and Smart industrial applications leads Fan Out Wafer Level Package (FOWLP) technologies to a promising solution to overcome the limitation of conventional wafer level package, flip chip package and wire bonding package in terms of the solution of low cost, high performance and smaller form factor packaging. Moreover, FOWLP technology can be extended to system-in-package (SiP) area, such as multi chip 2D package and 3D stack package types. nepes Corporation has developed several advanced package platforms such as single, multi dies and 2D, 3D packaging by using FOWLP and embedding technologies. To fulfill SiP (system-in-package) with FOWLP, several dies and components have been embedded into one package which offers 40~90 % of volumetric shrink compared to the current module system with the flexibility of product design for end users. 3D package technology of PoP (Package on Package) structure will be introduced for communication module and system control application.