Details

Autor(en) / Beteiligte

• Li, Y.-Q
• Wang, H.-B
• Liu, R.
• Chen, L.
• Nofal, I.
• Shi, S.-T
• He, A.-L
• Guo, G.
• Baeg, S. H.
• Wen, S.-J
• Wong, R.
• Chen, M.
• Wu, Q.

Titel

A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

Ist Teil von

• IEEE transactions on nuclear science, 2017-06, Vol.64 (6), p.1554-1561

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2017

Quelle

IEEE Xplore

Beschreibungen/Notizen

• A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits.