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2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, p.637-648
2017
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Autor(en) / Beteiligte
Titel
Processing-in-Memory Enabled Graphics Processors for 3D Rendering
Ist Teil von
  • 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, p.637-648
Ort / Verlag
IEEE
Erscheinungsjahr
2017
Quelle
IEEE/IET Electronic Library
Beschreibungen/Notizen
  • The performance of 3D rendering of Graphics Processing Unit that converts 3D vector stream into 2D frame with 3D image effects significantly impacts users gaming experience on modern computer systems. Due to its high texture throughput requirement, main memory bandwidth becomes a critical obstacle for improving the overall rendering performance. 3D-stacked memory systems such as Hybrid Memory Cube provide opportunities to significantly overcome the memory wall by directly connecting logic controllers to DRAM dies. Although recent works have shown promising improvement in performance by utilizing HMC to accelerate special-purpose applications, a critical challenge of how to effectively leverage its high internal bandwidth and computing capability in GPU for 3D rendering remains unresolved. Based on the observation that texel fetches greatly impact off-chip memory traffic, we propose two architectural designs to enable Processing-In-Memory based GPU for efficient 3D rendering. Additionally, we employ camera angles of pixels to control the performance-quality tradeoff of 3D rendering. Extensive evaluation across several real-world games demonstrates that our design can significantly improve the performance of texture filtering and 3D rendering by an average of 3.97X (up to 6.4X) and 43% (up to 65%) respectively, over the baseline GPU. Meanwhile, our design provides considerable memory traffic and energy reduction without sacrificing rendering quality.
Sprache
Englisch
Identifikatoren
eISSN: 2378-203X
DOI: 10.1109/HPCA.2017.37
Titel-ID: cdi_ieee_primary_7920862

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