Details

Autor(en) / Beteiligte

• Kim, Chulbum
• Cho, Ji-Ho
• Jeong, Woopyo
• Park, Il-han
• Park, Hyun-Wook
• Kim, Doo-Hyun
• Kang, Daewoon
• Lee, Sunghoon
• Lee, Ji-Sang
• Kim, Wontae
• Park, Jiyoon
• Ahn, Yang-lo
• Lee, Jiyoung
• Lee, Jong-hoon
• Kim, Seungbum
• Yoon, Hyun-Jun
• Yu, Jaedoeg
• Choi, Nayoung
• Kwon, Yelim
• Kim, Nahyun
• Jang, Hwajun
• Park, Jonghoon
• Song, Seunghwan
• Park, Yongha
• Bang, Jinbae
• Hong, Sangki
• Jeong, Byunghoon
• Kim, Hyun-Jin
• Lee, Chunan
• Min, Young-Sun
• Lee, Inryul
• Kim, In-Mo
• Kim, Sung-Hoon
• Yoon, Dongkyu
• Kim, Ki-Sung
• Choi, Youngdon
• Kim, Moosung
• Kim, Hyunggon
• Kwak, Pansuk
• Ihm, Jeong-Don
• Byeon, Dae-Seok
• Lee, Jin-yub
• Park, Ki-Tae
• Kyung, Kye-hyun

Titel

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory

Ist Teil von

• 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.202-203

Ort / Verlag

IEEE

Erscheinungsjahr

2017

Quelle

IEEE Xplore

Beschreibungen/Notizen

• The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014, the memory array size has nearly doubled every year. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.