Details

Autor(en) / Beteiligte

• Himchan Park
• Junan Lee
• Jinwoo Kim
• Yongsik Shin
• Jinwook Burm

Titel

High frame rate VGA CMOS image sensor using two-step single slope ADCs

Ist Teil von

• 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2016, p.571-572

Ort / Verlag

IEEE

Erscheinungsjahr

2016

Quelle

IEEE Xplore

Beschreibungen/Notizen

• A column-parallel two step Single Slope Analog-to-Digital Converter (SS ADC) for high frame rate VGA CMOS Image Sensor. The proposed circuit improves the sampling rate while maintaining the architecture of the conventional SS ADC for high frame rate CIS. The proposed structure does not have analog memory capacitor for storing the value of the first ramp step. The proposed two-step SS ADC has a 12bit resolution and conversion time of 6.3μs at 62.5MHz clock frequency. The VGA CIS using two step SS ADC has the maximum frame rate of up to 320 frames/s.