Details

Autor(en) / Beteiligte

• Xulong Tang
• Kandemir, Mahmut
• Yedlapalli, Praveen
• Kotra, Jagadish

Titel

Improving bank-level parallelism for irregular applications

Ist Teil von

• 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016, p.1-12

Ort / Verlag

IEEE

Erscheinungsjahr

2016

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Xplore

Beschreibungen/Notizen

• Observing that large multithreaded applications with irregular data access patterns exhibit very low memory bank-level parallelism (BLP) during their execution, we propose a novel loop iteration scheduling strategy built upon the inspector-executor paradigm. A unique characteristic of this strategy is that it considers both bank-level parallelism (from an inter-core perspective) and bank reuse (from an intra-core perspective) in a unified framework. Its primary goal is to improve bank-level parallelism, and bank reuse is taken into account only if doing so does not hurt bank-level parallelism. Our experiments with this strategy using eight application programs on both a simulator and a real multicore system show an average BLP improvement of 46.8% and an average execution time reduction of 18.3%.