Details

Autor(en) / Beteiligte

• Mishra, Shivshankar
• Mishra, Anjali
• Shastri, Anish
• Madhekar, Suneel

Titel

FPGA implementation of iterative decoder for turbo codes for software defined radio

Ist Teil von

• 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 2016, p.2357-2361

Ort / Verlag

IEEE

Erscheinungsjahr

2016

Quelle

IEEE Xplore

Beschreibungen/Notizen

• Implementation of iterative decoder for turbo codes is a challenging task; however, various algorithms have been proposed to enable the implementation of iterative decoder for turbo codes in a hardware device. For faster prototype development of any wireless communication system, software defined radio (SDR) is the best choice. This paper discusses the design and FPGA implementation of an iterative decoder for turbo codes using the MAX-LOG-MAP algorithm for an SDR. The entire implementation is carried out using the Xilinx block set available in MATLAB and SIMULINK. Xilinx System Generator is used to generate bit file which is used to configure Virtex-4 FPGA device in an SDR platform. BER plot and output results for the implementation are also presented.