Details

Autor(en) / Beteiligte

• Abassi, Oussama
• Conde-Canencia, Laura
• Al Ghouwayel, Ali
• Boutillon, Emmanuel

Titel

A Novel Architecture for Elementary-Check-Node Processing in Nonbinary LDPC Decoders

Ist Teil von

• IEEE transactions on circuits and systems. II, Express briefs, 2017-02, Vol.64 (2), p.136-140

Ort / Verlag

IEEE

Erscheinungsjahr

2017

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Xplore

Beschreibungen/Notizen

• This brief presents an efficient architecture design for elementary-check-node processing in nonbinary low-density parity-check decoders based on the extended min-sum algorithm. This architecture relies on a simplified version of the bubble check algorithm and is implemented by the means of first-in-first-out. The adoption of this new design at the check node level results in a high-rate low-cost full-pipelined processor. A proof-of-concept implementation of this processor shows that the proposed architecture halves the occupied the field-programmable gate array (FPGA) surface and doubles the maximum frequency without modifying the input/output behavior of the previous one.