Details

Autor(en) / Beteiligte

• Choi, Seungnam
• Son, Hyunwoo
• Shin, Jongshin
• Lee, Sang-Hyun
• Kim, Byungsub
• Park, Hong-June
• Sim, Jae-Yoon

Titel

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization

Ist Teil von

• IEEE transactions on circuits and systems. I, Regular papers, 2016-02, Vol.63 (2), p.276-287

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2016

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit with an asynchronous baud-rate sampling to achieve an adaptive equalization as well as a data rate acquisition. The proposed scheme also enables the use of a successive approximation register (SAR) based approach in the frequency acquisition and results in a fast coarse lock process. The CDR guarantees a robust operation of a fine locking even in the presence of large input data jitter due to the adaptive equalization and a jitter-tolerable rotation frequency detector (RFD) that eliminates a dead-zone problem with a simple circuitry. The fabricated CDR in 65 nm CMOS shows a wide lock range of 0.65-to-10.5 Gb/s at a bit error rate (BER) of 10 -12 . The CDR consumes 26 mW from a single supply voltage of 1 V at 10 Gb/s including the power consumption for equalizer. By an adaptive current bias control, the power consumption is also linearly scaled down with the data rate, exhibiting a slope of about 2 mW decrease per Gb/s.