Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015, p.1-7
2015
Volltextzugriff (PDF)

Details

Autor(en) / Beteiligte
Titel
Feasibility of high level compiler optimizations in online synthesis
Ist Teil von
  • 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015, p.1-7
Ort / Verlag
IEEE
Erscheinungsjahr
2015
Quelle
IEEE Electronic Library Online
Beschreibungen/Notizen
  • High-level synthesis approaches are currently very popular. They use specifications on rather high abstraction levels like C or SystemC to describe the required system functionality and automatically generate a hardware implementation for this specification. Shifting this process to the runtime of the system leads to so called online synthesis. The advantage of this approach is that only heavily used parts for the current run of the software need to be synthesized and also profiling information of the current run can be used to optimize the implementation, which enables an adaptive system behavior. Additionally, synthesis will only use the amount of currently available resources. Obviously, in this case the synthesis algorithms must run sufficiently fast such that the hardware implementation is created quickly enough. In this contribution we discuss the feasibility and the efficiency of different high-level optimizations which are usually performed by sophisticated compilers and synthesis systems.
Sprache
Englisch
Identifikatoren
DOI: 10.1109/ReConFig.2015.7393310
Titel-ID: cdi_ieee_primary_7393310

Weiterführende Literatur

Empfehlungen zum selben Thema automatisch vorgeschlagen von bX