2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015, p.1-3
2015
Volltextzugriff (PDF)
Details
- Autor(en) / Beteiligte
- Titel
- Impact of source/drain silicon cap on FDSOI SiGe pMOSFET performance
- Ist Teil von
- 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015, p.1-3
- Ort / Verlag
- IEEE
- Erscheinungsjahr
- 2015
- Quelle
- IEEE Xplore
- Beschreibungen/Notizen
- This paper analyses the impact of 10nm Si cap layer for UTBB pFET eSiGe, with 35% Ge in channel and source/drain. For the first time, it is found that this Si cap can improve both access resistance and hole mobility in narrow structures.
- Sprache
- Englisch
- Identifikatoren
- DOI: 10.1109/S3S.2015.7333544Titel-ID: cdi_ieee_primary_7333544
- Format
- –
- Schlagworte
- embedded SiGe, FDSOI, Logic gates, Performance evaluation, Silicon, silicon cap, Silicon germanium, Stress, Uniaxial strain, UTBB