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A focus on region yield is demonstrated to improve the systematic yield from 75% to the upper 90% to achieve a quick learning curve in defect density on new products. A learning curve to drive both the random and systematic yield simultaneously are important to accelerate the yield learning on new products as well as on existing products. This paper showed the systematic yield improvement from a module integration issue to an equipment set-up and capability issue. A new methodology has been defined to look at the wafer edge region, and is used to address wafer edge issues with systematic approaches to drive yield improvement. The process variability on the center of the wafer is low, but as one approaches the edge of the wafer, large process variations arise which depress the yield at the edge of the wafers. This decrease in yield can be caused by technology architecture, process uniformity, wafer misalignment and mark alignment scheme issues.