Details

Autor(en) / Beteiligte

• Sakuma, Katsuyuki
• Tunga, Krishna
• Webb, Buck
• Ramachandran, Koushik
• Interrante, Marcus
• Hsichang Liu
• Angyal, Matthew
• Berger, Daniel
• Knickerbocker, John
• Iyer, Subramanian

Titel

An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates

Ist Teil von

• 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015, p.318-324

Ort / Verlag

IEEE

Erscheinungsjahr

2015

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• In this work, a controlled thermo-compression (TC) bonding process has been developed to address problems caused by interposer and laminate warpage when assembling large three-dimensional (3D) integrated circuit (IC) die on an organic substrate (laminate). By using TC bonding, a thin interposer with through-silicon-vias (TSV) is joined to a top die while being held flat by vacuum and vertical pressure. A vacuum distribution plate is developed and used to mitigate warpage during 3D assembly. A unique set of process parameters has been developed which enables the joining of severely bowed, large area interposers to a semiconductor die without C4 (Controlled Collapse Chip Connection) shorting. The controlled TC bonding method developed in this work offers a huge advantage when joining multiple large warped die in a stack. This evaluation used a large 22 nm CMOS top die with ultra low-K (ULK) back end of the line (BEOL) and copper pillar/SnAg solder bumps at two different pitch sizes, 61 μm and 131 μm. Both the top die and interposer die were larger than 600 mm 2 while the organic substrate was 68.5 mm × 68.5 mm. The top die and interposer were bonded with parameters developed for an enhanced TC bonding process. Cross-sectional analysis of the 3D assembly showed that the solder joints along the perimeter of chips exhibited good joining with good solder wettability and no solder bridging. Non-destructive X-ray analysis also confirmed that there were no C4 bump bridging across the entire chip area. The experimental results verified that the enhanced TC bonding process can effectively prevent C4 bump bridging and C4 bump electrical opens for a large die packaged in a 3D configuration with a highly warped large area silicon interposer.