Details

Autor(en) / Beteiligte

• Merchant, Farhad
• Maity, Arka
• Mahadurkar, Mahesh
• Vatwani, Kapil
• Munje, Ishan
• Krishna, Madhava
• Nalesh, S.
• Gopalan, Nandhini
• Raha, Soumyendu
• Nandy, S. K.
• Narayan, Ranjani

Titel

Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations

Ist Teil von

• 2015 28th International Conference on VLSI Design, 2015, p.153-158

Ort / Verlag

IEEE

Erscheinungsjahr

2015

Quelle

IEEE Xplore

Beschreibungen/Notizen

• LU and QR factorizations are the computationally dear part of many applications ranging from large scale simulations (e.g. Computational fluid dynamics) to augmented reality. These factorizations exhibit time complexity of O (n 3 ) and are difficult to accelerate due to presence of bandwidth bound kernels, BLAS-1 or BLAS-2 (level-1 or level-2 Basic Linear Algebra Subprograms) along with compute bound kernels (BLAS-3, level-3 BLAS). On the other hand, Coarse Grained Reconfigurable Architectures (CGRAs) have gained tremendous popularity as accelerators in embedded systems due to their flexibility and ease of use. Provisioning these accelerators in High Performance Computing (HPC) platforms is the research challenge wrestled by the computer scientists. We consider a CGRA environment in which several Compute Elements (CEs) enhanced with Custom Functional Units (CFUs) are interconnected over a Network-on-Chip (NoC). In this paper, we carry out extensive micro-architectural exploration for accelerating core kernels like Matrix Multiplication (MM) (BLAS-3) for LU and QR factorizations. Our 5 different design enhancements lead to the reduction in the latency of BLAS-3 kernels. On a stand-alone CFU, we achieve up to 8x speed-up for MM. A commensurate improvement is observed for MM in a CGRA environment. We achieve better GF LOP S/mm 2 compared to recent implementations.