Details

Autor(en) / Beteiligte

• Wai-Chi Fang
• Kuan-Ju Huang
• Chia-Ching Chou
• Jui-Chung Chang
• Cauwenberghs, Gert
• Tzyy-Ping Jung

Titel

An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system

Ist Teil von

• 2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014, Vol.2014, p.3849-3852

Ort / Verlag

United States: IEEE

Erscheinungsjahr

2014

Quelle

IEEE Xplore

Beschreibungen/Notizen

• This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.