Details

Autor(en) / Beteiligte

• Jun-Sang Park
• Tai-Ji An
• Yong-Min Kim
• Suk-Hee Cho
• Hyun-Sun Shim
• Woo-Jin Jang
• Yong-Jin Shin
• Jun-Hyup Lee
• Gil-Cho Ahn
• Seung-Hoon Lee

Titel

A 10b 50MS/s 90nm CMOS skinny-shape ADC using variable references for CIS applications

Ist Teil von

• 2013 International SoC Design Conference (ISOCC), 2013, p.080-082

Ort / Verlag

IEEE

Erscheinungsjahr

2013

Quelle

IEEE/IET Electronic Library (IEL)

Beschreibungen/Notizen

• This work proposes a skinny-shape 10b 50MS/s 90nm CMOS four-step pipeline ADC for various CIS applications. The proposed ADC converts analog signals in variable signal-swing ranges of 1.12 to 1.60Vp-p into low voltage-based digital data. The proposed on-chip I/V reference circuits generate the required variable reference voltages with a fixed common-mode level using a single external control voltage. The prototype ADC implemented in a 90nm CMOS process shows a maximum SNDR and SFDR of 55.1dB and 65.6dB, respectively. The ADC with an active die area of 0.23mm 2 consumes 17.5mW at 50MS/s using dual supply voltages of 2.5V for analog and 1.2V for digital.