Details

Autor(en) / Beteiligte

• Tokunaga, Carlos
• Ryan, Joseph F.
• Augustine, Charles
• Kulkarni, Jaydeep P.
• Yi-Chun Shih
• Kim, Stephen T.
• Jain, Rinkle
• Bowman, Keith
• Raychowdhury, Arijit
• Khellah, Muhammad M.
• Tschanz, James W.
• De, Vivek

Titel

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep

Ist Teil von

• 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.108-109

Ort / Verlag

IEEE

Erscheinungsjahr

2014

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• In this paper, we present a low-power graphics processing core that achieves a 40% improvement in peak energy efficiency using dual-VCC arrays, adaptive clocking for voltage droop mitigation, and state retention capability with an integrated retention clamping circuit for low-power sleep mode. The 22nm testchip includes a graphics execution core connected to an SRAM array and test controller used for storage and delivery of at-speed test vectors. Correct execution of the tests is validated through a multiple-input signature register (MISR), which accumulates key signals in the core and generates a 32b signature at test completion.