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High throughput Cholesky decomposition based on FPGA
Ist Teil von
2013 6th International Congress on Image and Signal Processing (CISP), 2013, Vol.3, p.1649-1653
Ort / Verlag
IEEE
Erscheinungsjahr
2013
Link zum Volltext
Quelle
IEEE Xplore
Beschreibungen/Notizen
Cholesky decomposition has wide applications in solving many engineering and scientific problems. Acceleration is an important issue in many of these problems. In this paper, a hardware-based LL T Cholesky decomposition featuring high throughput has been presented to solve wiener filtering based on the minimum square error criterion. To achieve the best efficiency, the hardware-based implementation has been realized by fixed-point multiple structures and various pipeline stages. Parallel properties have been exploited to improve the throughput. Results have shown that a significant speedup has been achieved compared to the software-based approach.