Details

Autor(en) / Beteiligte

• Callemeyn, Piet
• Steyaert, Michiel

Titel

A stacked full-bridge topology for high voltage DC-AC conversion in standard CMOS technology

Ist Teil von

• 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013, p.65-68

Ort / Verlag

IEEE

Erscheinungsjahr

2013

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• A monolithic DC-AC converter is realized in a 130 nm 1.2V CMOS technology using a Class-D half-bridge topology. Several dies are combined to achieve a full-bridge topology, realizing a bipolar output voltage. Using a stacking technique, this output voltage can be increased. This yields AC output voltages up to 4V, which is more than three times the nominal 1.2V supply voltage of the technology. The passives are integrated on-chip. Consequently, the bill of materials (BOM) is heavily reduced. In a standard half-bridge topology, bulky external capacitors are needed to filter out the DC offset. This main obstacle of an off-chip capacitor is alleviated in the full-bridge topology, reducing the BOM even more. An output peak-to-peak voltage of 3.8V is achieved at a maximal efficiency of 58.3%. A total output power of 56mW is obtained.