Details

Autor(en) / Beteiligte

• Veloso, A.
• Boccardi, G.
• Ragnarsson, L.-A
• Higuchi, Y.
• Lee, J. W.
• Simoen, E.
• Roussel, Ph J.
• Cho, M. J.
• Chew, S. A.
• Schram, T.
• Dekkers, H.
• Van Ammel, A.
• Witters, T.
• Brus, S.
• Dangol, A.
• Paraschiv, V.
• Vecchio, E.
• Shi, X.
• Sebaai, F.
• Kellens, K.
• Heylen, N.
• Devriendt, K.
• Richard, O.
• Bender, H.
• Chiarella, T.
• Arimura, H.
• Thean, A.
• Horiguchi, N.

Titel

Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodes

Ist Teil von

• 2013 Symposium on VLSI Technology, 2013, p.T194-T195

Ort / Verlag

IEEE

Erscheinungsjahr

2013

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• We report on a novel EWF engineering approach enabling wide V T modulation in aggressively scaled RMG-HKL planar and multi-gate FinFET-based devices with high aspect-ratio gate trenches. Key features include: 1) Al diffusion control from fill-metal (Co x Al y ) through an ultra-thin TaN layer on HfO 2 /TiN and fine-tuned TiN/ TaN thicknesses; 2) optimized TiN films for enhanced (NMOS) or inhibited (PMOS) Al diffusion through it. For a total TiN/TaN thickness of less than 2.5nm, low-V T NMOS planar bulk devices with σ(V T )~14mV at L gate ~30nm and A VT ~1.98mV.μm are obtained. By increasing the bi-layer thickness to ~4nm a ~130mV higher V T is achieved with no J G nor EOT impact, and with the use of PDA resulting in an attractive ~10× J G reduction. >500mV ΔV T in narrow fin, triple-gate FinFETs (W Fin ≥5nm) enable low-V T NMOS with improved mobility and BTI, up to ~6.3× reduced noise, and J G ~0.16/1.9A/cm 2 at 1V, 9Å EOT for V Tlin =0.29/0.11V, respectively.