Details

Autor(en) / Beteiligte

• Kuan-Ju Huang
• Jui-Chung Chang
• Chih-Wei Feng
• Wai-Chi Fang

Titel

A parallel VLSI architecture of singular value decomposition processor for real-time multi-channel EEG system

Ist Teil von

• 2013 IEEE International Symposium on Consumer Electronics (ISCE), 2013, p.21-22

Ort / Verlag

IEEE

Erscheinungsjahr

2013

Quelle

IEEE Xplore

Beschreibungen/Notizen

• This paper presents a parallel VLSI architecture of a singular value decomposition (SVD) processor for real-time multi-channel electroencephalography (EEG) System. In the recent years, EEG has been widely applied on engineering research, medical diagnosis, and so on. More and more studies regarding brain-computer interface (BCI) and other related applications have been published. In order to increase the accuracy of BCI, the need for a real-time multi-channel EEG System is very urgent. Because an EEG system uses a SVD processor to calculate inverse matrix of target ones, the real-time requirement of the EEG system depends on the operation latency of the SVD processor. Moreover, the accuracy of results obtained from SVD processor directly affects the performance of the system. Generally, SVD is based on coordinate rotation digital computer (CORDIC) algorithm in hardware implementation. Therefore, there is a trade-off between the iteration number of the CORDIC engine, which is related to the computing latency of the SVD processor, and accuracy of SVD the results. In this paper, the parallel architecture of the SVD processor can efficiently shorten the clock cycle of iteration times and provide a precise inverse matrix result. This work not only upgrades the EEG system practicability, but also ensures the feasibility of real-time application. The proposed SVD processor is implemented in the 8-channel EEG system using the TSMC 90 nm CMOS technology.