Details

Autor(en) / Beteiligte

• Pereira, V. F.
• Moreno, E. D.
• Dias, W. R. A.
• q, Dellano O. D.

Titel

Specific processor in FPGA for BLAKE algorithm

Ist Teil von

• 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), 2013, p.1-5

Ort / Verlag

IEEE

Erscheinungsjahr

2013

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Xplore Digital Library

Beschreibungen/Notizen

• This article presents the analysis of assembly instructions from SHA-3 BLAKE algorithm, running on an ARM® processor, with the intention of developing a specific processor in FPGA for BLAKE Algorithm. For this purpose, we have used an implementation in C of the algorithm, where we could discover which instructions were executed and how frequently they have appeared on the code, making use of the SimpleScalar architectural simulation tool. Moreover, we have utilized VHDL. The Synthesis and simulations of the ALU and UC, developed in this article, were done with the usage of the ALTERA ® Quartus-II 9.1. Our VHDL implementation with all 27 instructions executed on BLAKE algorithm occupied 43% of the FPGA's area, presenting a small delay of just 24ns, and the processor had a 4.8 CPI value.