Details

Autor(en) / Beteiligte

• Aziz, R. M. F. T.
• Baharim, R.
• Nasir, M. H. M.
• Wahab, R. A.
• Othman, N.
• Razali, N.
• Saleh, S.

Titel

Methodology To execute SPARC binary of Silterra memory compiler 0.18um process technology on x86 Architecture

Ist Teil von

• 2012 10th IEEE International Conference on Semiconductor Electronics (ICSE), 2012, p.475-477

Ort / Verlag

IEEE

Erscheinungsjahr

2012

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• This paper addresses the issue of Silterra memory compiler 0.18 micrometer (um) technology that can only be run with Solaris operating system with Scalable Processor Architecture (SPARC). However, a lot of technologies in software applications had moved to x86 platforms. SUN, which produced SPARC machines, also had merged into ORACLE, a database expert company. Today it is hard to find support for SPARC machines, as most developers now are moving to x86 operating system with Intel architecture. This paper proposes a solution by using QEMU approach. QEMU stands for "Quick Emulator" which emulates the role of SPARC machines that installs Solaris operating system with SPARC architecture on Linux machines. Now, the Silterra memory compiler 0.18um process can be executed on the virtual machine, as it recognizes the platform as Solaris SPARC architecture. This methodology not only for memory compiler of 0.18um Silterra but also can be use for others SPARC binaries.