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The SPARC T4 processor introduces the next generation multi-threaded 64b core to deliver up to 5x integer and 7x floating-point single-thread performance improvement over its predecessor. The chip integrates eight cores, an 8-Bank 4 MB L3 Cache, a 768 GB/sec crossbar, a memory controller, PCI Gen2.0, 10 Gb Ethernet and cache coherency with 2.4 Tb/s bandwidth high-speed I/Os. The dual-issue, out-of-order execution core (S3) features a new 16-stage integer pipeline, extensive branch predictions, dynamic threading and an enhanced cryptographic processing unit. The 406 mm ^{2} die contains 855 million transistors and 2.6 million flip-flops in TSMC's 40nm process utilizing 11 Cu metals and four transistor types. Enhanced physical design methodologies and extensive power management features enable 3.0 GHz operation in the same power envelope of its predecessor. Logically complex SRAMs deploy techniques to support out-of-order execution core while addressing area, timing and power challenges. The power supply calibration circuit improves yield by reducing 70% of conventional voltage guard-band for the speed and power constrained design.