Details

Autor(en) / Beteiligte

• Chen, J. H.-C
• Waskiewicz, C.
• Fan, S. S.-C
• Halle, S.
• Chiew-seng Koay
• Yongan Xu
• Saulnier, N.
• Chia-Hsun Tseng
• Yunpeng Yin
• Mignot, Y.
• Beard, M.
• Morris, B.
• Horak, D.
• Mignot, S.
• Shobha, H.
• Sankarapandian, M.
• van der Straten, O.
• Kelly, J. J.
• Canaperi, D.
• Mclellan, E.
• Boye, C.
• Levin, T.
• Juntao Li
• Demarest, J.
• Choi, S.
• Huang, E.
• Liemann, L.
• Haran, B.
• Arnold, J. C.
• Colburn, M.
• Clevenger, L.
• Spooner, T.

Titel

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

Ist Teil von

• 2012 IEEE International Interconnect Technology Conference, 2012, p.1-3

Ort / Verlag

IEEE

Erscheinungsjahr

2012

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the advanced logic circuits. The patterning scheme is multiple negative tone development lithography-etch. A memorization layer is utilized in the triple patterned M1 and the double patterned V0 levels, respectively. After transferring the two via levels into the metal memorization layer, a self-aligned-via (SAV) RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. Seven litho/etch steps (LIP1/LIP2/V0C1/V0C2/M1P1/M1P2/M1P3) were employed to present this revolutionary interconnects.