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2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011, p.367-370
2011
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Autor(en) / Beteiligte
Titel
Efficent low cost process for single step metal forming of 3D interconnected above-IC inductors
Ist Teil von
  • 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011, p.367-370
Ort / Verlag
IEEE
Erscheinungsjahr
2011
Quelle
IEEE Xplore
Beschreibungen/Notizen
  • This paper presents a novel and efficient low cost process capable of integrating high-Q above-IC inductors and their interconnects using a single electroplating step. It relies on the SU8 and BPN resist as well as an optimized electroplating technique to form the 3D interconnected inductor. The SU8 is used to form a thick layer located underneath the inductor to elevate it from the substrate. Then, the BPN is used as a high resolution mold (16:1) for copper electroplating. Standard or time optimized electroplating is later used to grow copper in a 3D manner, making the transition between all metallic layers straight forward. High-Q (55 @ 5 GHz) power inductors have been designed and integrated above an RF power LDMOS device using this process. Finally, the process capabilities are demonstrated by integrating a solenoid inductor using only two lithography masks and a single electroplating step.
Sprache
Englisch
Identifikatoren
ISBN: 9781457707070, 1457707071
ISSN: 1930-8876
DOI: 10.1109/ESSDERC.2011.6044158
Titel-ID: cdi_ieee_primary_6044158

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