Details

Autor(en) / Beteiligte

• Li, Ye
• Yao, Qingming
• Tian, Bin
• Xu, Wencong

Titel

Fast double-parallel image processing based on FPGA

Ist Teil von

• Proceedings of 2011 IEEE International Conference on Vehicular Electronics and Safety, 2011, p.97-102

Ort / Verlag

IEEE

Erscheinungsjahr

2011

Quelle

IEEE Xplore

Beschreibungen/Notizen

• Due to FPGA's flexibility and parallelism, it is popular for accelerating image processing. In this paper, a double-parallel architecture based on FPGA has been exploited to speed up median filter and edge detection tasks, which are essential steps during image processing. The double-parallel scheme includes an image-level parallel and an operation-level parallel. The image-level parallel is a high-level parallel which divides one image into different parts and processes them concurrently. The operation-level parallel, which is embedded in each image-level parallel thread, fully explores every parallel part inside the concrete algorithms. The corresponding design is based on a DE2 Development Board which contains a CYCLONE II FPGA device. Meanwhile, the same task has also been implemented on PC and DSP for performance comparison. Despite the fact that operating frequencies of used PC and DSP are much higher than FPGA's, FPGA costs less time per computed image than both of them. By taking advantage of the double-parallel technique, the speed/frequency ratio of FPGA is 202 times faster than PC and 147 times faster than DSP. Finally, a detailed discussion about different platforms is conducted, which analyzes advantages and disadvantages of used computing platforms. This paper reveals that the proposed double-parallel scheme can dramatically speed up image processing methods even on a low-cost FPGA platform with low frequency and limited resources, which is very meaningful for practical applications.