Details

Autor(en) / Beteiligte

• Shyng-Tsong Chen
• Tomizawa, H.
• Tsumura, K.
• Tagami, M.
• Shobha, H.
• Sankarapandian, M.
• Van der Straten, O.
• Kelly, J.
• Canaperi, D.
• Levin, T.
• Cohen, S.
• Yin, Y.
• Horak, D.
• Ishikawa, M.
• Mignot, Y.
• Koay, C.-S
• Burns, S.
• Halle, S.
• Kato, H.
• Landie, G.
• Xu, Y.
• Scaduto, A.
• Mclellan, E.
• Arnold, J. C.
• Colburn, M.
• Usui, T.
• Spooner, T.

Titel

64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme

Ist Teil von

• 2011 IEEE International Interconnect Technology Conference, 2011, p.1-3

Ort / Verlag

IEEE

Erscheinungsjahr

2011

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• This work demonstrates the building of 64 nm pitch copper single and dual damascene interconnects using pitch split double patterning scheme to enable sub 80 nm pitch patterning. A self-aligned-via (SAV) litho/RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. An undercut free post RIE trench profile enabled the good metal fill. Initial reliability test result and the possibility of using the same scheme for 56 nm pitch interconnects are also discussed.