Details

Autor(en) / Beteiligte

• Sun Hui
• Guo Jing
• Wang Jiajing
• Zhang Qianling

Titel

A 1.8-V 64-kb four-way set-associative CMOS cache memory using fast sense amplifier and split dynamic tag comparators

Ist Teil von

• ASIC, 2003. Proceedings. 5th International Conference on, 2003, Vol.1, p.474-477 Vol.1

Ort / Verlag

IEEE

Erscheinungsjahr

2003

Quelle

IEEE/IET Electronic Library (IEL)

Beschreibungen/Notizen

• This paper reports a 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18 μm 1.8 V 1P6M logic CMOS technology. This cache is designed for a 32-b RISC microprocessor. Effective latency of 3.4 ns and power consumption of 190 mW at 263 MHz are obtained at a supply voltage of 1.8 V. This performance is achieved by using high speed circuit design techniques such as modified high speed current-mode sense amplifier and split dynamic tag comparators.